For example, DRAM in embedded dynamic random access memory (eDRAM) includes a plurality of word lines extending, for example, in a first direction on a main surface of a semiconductor substrate, a plurality of bit lines extending in a second direction intersecting with the first direction, and a plurality of DRAM cells each disposed at an intersection between the word line and the bit line and electrically connected to the word line and the bit line.
The DRAM cell is constituted by one selection metal insulator field effect transistor (MISFET) and one capacitive element connected in series to the selection MISFET. The selection MISFET is constituted by a gate electrode integrally formed with the word line, and semiconductor regions serving as a source and a drain, respectively. One of the source and the drain is connected to the bit line, and the other is electrically connected to the capacitive element.
The logic circuit is constituted by a p-channel MISFET (pMISFET) and an n-channel MISFET (nMISFET). The pMISFET has a gate electrode and p-type semiconductor regions serving as a source and a drain, respectively, and the nMISFET has a gate electrode and n-type semiconductor regions serving as a source and a drain, respectively.
In general, in a MISFET constituting a logic circuit (hereinafter referred to as a logic MISFET), a feed-forward technique has been studied in manufacturing processes in order to improve electrical characteristics of the MISFET.
Japanese Patent Application Laid-Open Publication No. 2006-108498 discloses that dimensions of a formed gate electrode 102 are measured in order to suppress variations in element characteristics due to variations in dimensions of the gate electrode, and ion implantation conditions for a drain extension region 104 are set according to the measured dimensions.
Japanese Patent Application Laid-Open Publication No. 2001-196580 discloses that a length of a formed gate electrode is measured in order to preferably control transistor characteristics regarding a short-channel effect, and a dosage of ion implantation is variably set in order to form a source region and a drain region according to the measured value.
Japanese Patent Application Laid-Open Publication No. 2001-308317 discloses that a length of a formed gate electrode is measured in order to make transistor characteristics uniform, and a dosage for an SD extension region or a pocket region is adjusted according to the measured value.
Japanese Patent Application Laid-Open Publication No. 2008-28217 discloses that a resistance value of an impurity region 5p having the same level of impurity concentration as that of a first source/drain region 5 is measured, and an impurity concentration for forming a second source/drain region 7 is changed according to the measured value.
Japanese Patent Application Laid-Open Publication No. 2001-332723 discloses that electrical characteristics of a formed semiconductor element are tested in order to form a semiconductor element having characteristics close to design values, conditions for a coating covering the semiconductor element are determined according to the test result, and the coating is formed so as to meet the conditions.